[PATCH 2/3] Fix cpuid vendor-id check for i386 and x86-64

[Jussi Kivilinna]

detect_x86_64_gnuc() and detect_ia32_gnuc() incorrectly exclude Intel
features on all other vendor CPUs. What we want here, is to detect if
CPU from any vendor support said Intel feature (in this case AES-NI).

Signed-off-by: Jussi Kivilinna <jussi.kivilinna at mbnet.fi>
---
 src/hwfeatures.c |   59 +++++++++++++++++++++++++++++-------------------------
 1 file changed, 32 insertions(+), 27 deletions(-)

diff --git a/src/hwfeatures.c b/src/hwfeatures.c
index 456c07a..606f3e7 100644
--- a/src/hwfeatures.c
+++ b/src/hwfeatures.c
@@ -112,24 +112,26 @@ detect_x86_64_gnuc (void)
   else if (!strcmp (vendor_id, "GenuineIntel"))
     {
       /* This is an Intel CPU.  */
-      asm volatile
-        ("movl $1, %%eax\n\t"           /* Get CPU info and feature flags.  */
-         "cpuid\n"
-         "testl $0x02000000, %%ecx\n\t" /* Test bit 25.  */
-         "jz .Lno_aes%=\n\t"            /* No AES support.  */
-         "orl $256, %0\n"               /* Set our HWF_INTEL_AES bit.  */
-
-         ".Lno_aes%=:\n"
-         : "+r" (hw_features)
-         :
-         : "%eax", "%ebx", "%ecx", "%edx", "cc"
-         );
     }
   else if (!strcmp (vendor_id, "AuthenticAMD"))
     {
       /* This is an AMD CPU.  */
-
     }
+
+  /* Detect Intel features, that might be supported also by other vendors
+   * also. */
+  asm volatile
+    ("movl $1, %%eax\n\t"           /* Get CPU info and feature flags.  */
+     "cpuid\n"
+     "testl $0x02000000, %%ecx\n\t" /* Test bit 25.  */
+     "jz .Lno_aes%=\n\t"            /* No AES support.  */
+     "orl $256, %0\n"               /* Set our HWF_INTEL_AES bit.  */
+
+     ".Lno_aes%=:\n"
+     : "+r" (hw_features)
+     :
+     : "%eax", "%ebx", "%ecx", "%edx", "cc"
+     );
 }
 #endif /* __x86_64__ && __GNUC__ */
 
@@ -237,26 +239,29 @@ detect_ia32_gnuc (void)
   else if (!strcmp (vendor_id, "GenuineIntel"))
     {
       /* This is an Intel CPU.  */
-      asm volatile
-        ("pushl %%ebx\n\t"	        /* Save GOT register.  */
-         "movl $1, %%eax\n\t"           /* Get CPU info and feature flags.  */
-         "cpuid\n"
-         "popl %%ebx\n\t"	        /* Restore GOT register. */
-         "testl $0x02000000, %%ecx\n\t" /* Test bit 25.  */
-         "jz .Lno_aes%=\n\t"            /* No AES support.  */
-         "orl $256, %0\n"               /* Set our HWF_INTEL_AES bit.  */
-
-         ".Lno_aes%=:\n"
-         : "+r" (hw_features)
-         :
-         : "%eax", "%ecx", "%edx", "cc"
-         );
     }
   else if (!strcmp (vendor_id, "AuthenticAMD"))
     {
       /* This is an AMD CPU.  */
 
     }
+
+  /* Detect Intel features, that might be supported also by other vendors
+   * also. */
+  asm volatile
+    ("pushl %%ebx\n\t"	        /* Save GOT register.  */
+     "movl $1, %%eax\n\t"           /* Get CPU info and feature flags.  */
+     "cpuid\n"
+     "popl %%ebx\n\t"	        /* Restore GOT register. */
+     "testl $0x02000000, %%ecx\n\t" /* Test bit 25.  */
+     "jz .Lno_aes%=\n\t"            /* No AES support.  */
+     "orl $256, %0\n"               /* Set our HWF_INTEL_AES bit.  */
+
+     ".Lno_aes%=:\n"
+     : "+r" (hw_features)
+     :
+     : "%eax", "%ecx", "%edx", "cc"
+     );
 }
 #endif /* __i386__ && SIZEOF_UNSIGNED_LONG == 4 && __GNUC__ */