master branch: SIGILL, Illegal instruction.

[jukivili]

Hello,

NIIBE Yutaka kirjoitti 2019-07-15 08:28:
> Hello,
> 
> It seems that vmovdqa instruction is not supported by all processors.

Right, that vmovdqa is AVX instruction and should not be used in 
_gcry_sha1_transform_amd64_ssse3. Correct instruction here is 'movdqa'. 
I can fix this later this week when I'm back home.

-Jussi

> 
> On my machine (Acer Chromebook C720) with:
> ==========================  One of processors:
> processor	: 0
> vendor_id	: GenuineIntel
> cpu family	: 6
> model		: 69
> model name	: Intel(R) Celeron(R) 2955U @ 1.40GHz
> stepping	: 1
> microcode	: 0x25
> cpu MHz		: 920.937
> cache size	: 2048 KB
> physical id	: 0
> siblings	: 2
> core id		: 0
> cpu cores	: 2
> apicid		: 0
> initial apicid	: 0
> fpu		: yes
> fpu_exception	: yes
> cpuid level	: 13
> wp		: yes
> flags		: fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov
> pat pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm pbe syscall nx
> pdpe1gb rdtscp lm constant_tsc arch_perfmon pebs bts rep_good nopl
> xtopology nonstop_tsc cpuid aperfmperf pni pclmulqdq dtes64 monitor
> ds_cpl vmx est tm2 ssse3 sdbg cx16 xtpr pdcm pcid sse4_1 sse4_2 movbe
> popcnt tsc_deadline_timer xsave rdrand lahf_lm abm cpuid_fault epb
> invpcid_single pti ssbd ibrs ibpb stibp tpr_shadow vnmi flexpriority
> ept vpid ept_ad fsgsbase tsc_adjust erms invpcid xsaveopt dtherm arat
> pln pts md_clear flush_l1d
> bugs		: cpu_meltdown spectre_v1 spectre_v2 spec_store_bypass l1tf mds
> bogomips	: 2793.74
> clflush size	: 64
> cache_alignment	: 64
> address sizes	: 39 bits physical, 48 bits virtual
> power management:
> ==========================
> 
> Starting program: /home/gniibe/work/build-libgcrypt/tests/t-mpi-bit
> 
> Program received signal SIGILL, Illegal instruction.
> _gcry_sha1_transform_amd64_ssse3 () at
> ../../libgcrypt/cipher/sha1-ssse3-amd64.S:404
> 404	  vmovdqa Wtmp0, (3*16)(%rsp);