[PATCH] poly1305: fix building with 'arm-linux-gnueabihf-gcc-11 -O3'

Jussi Kivilinna jussi.kivilinna at iki.fi
Mon Oct 25 19:55:20 CEST 2021


* cipher/poly1305.c [HAVE_COMPATIBLE_GCC_ARM_PLATFORM_AS]
(ADD_1305_32): Reduce number of register operands.
--

Ubuntu 21.10 arm-linux-gnueabihf-gcc gave following error with -O3:

poly1305.c: In function '_gcry_poly1305_update_burn':
cipher/poly1305.c:425:7: error: 'asm' operand has impossible constraints
  425 |       ADD_1305_32(h4, h3, h2, h1, h0, m4, m3, m2, m1, m0);
      |       ^

Signed-off-by: Jussi Kivilinna <jussi.kivilinna at iki.fi>
---
 cipher/poly1305.c | 32 +++++++++++++++++++++++++++-----
 1 file changed, 27 insertions(+), 5 deletions(-)

diff --git a/cipher/poly1305.c b/cipher/poly1305.c
index 41e55e8d..e57e64f3 100644
--- a/cipher/poly1305.c
+++ b/cipher/poly1305.c
@@ -298,15 +298,37 @@ static unsigned int poly1305_final (poly1305_context_t *ctx,
 	       : "0" (HI), "1" (LO), "r" (A), "r" (B) )
 
 /* A += B (arm) */
-#define ADD_1305_32(A4, A3, A2, A1, A0, B4, B3, B2, B1, B0) \
+#ifdef __GCC_ASM_FLAG_OUTPUTS__
+#  define ADD_1305_32(A4, A3, A2, A1, A0, B4, B3, B2, B1, B0) do { \
+      u32 __carry; \
       __asm__ ("adds %0, %0, %5\n" \
 	       "adcs %1, %1, %6\n" \
 	       "adcs %2, %2, %7\n" \
 	       "adcs %3, %3, %8\n" \
-	       "adc %4, %4, %9\n" \
-	       : "+r" (A0), "+r" (A1), "+r" (A2), "+r" (A3), "+r" (A4) \
-	       : "r" (B0), "r" (B1), "r" (B2), "r" (B3), "r" (B4) \
-	       : "cc" )
+	       : "+r" (A0), "+r" (A1), "+r" (A2), "+r" (A3), \
+	         "=@cccs" (__carry) \
+	       : "r" (B0), "r" (B1), "r" (B2), "r" (B3) \
+	       : ); \
+      (A4) += (B4) + __carry; \
+    } while (0)
+#else
+#  define ADD_1305_32(A4, A3, A2, A1, A0, B4, B3, B2, B1, B0) do { \
+      u32 __carry = (B0); \
+      __asm__ ("adds %0, %0, %2\n" \
+	       "adcs %1, %1, %3\n" \
+	       "rrx %2, %2\n" /* carry to 31th bit */ \
+	       : "+r" (A0), "+r" (A1), "+r" (__carry) \
+	       : "r" (B1), "r" (0) \
+	       : "cc" ); \
+      __asm__ ("lsls %0, %0, #1\n" /* carry from 31th bit */ \
+	       "adcs %1, %1, %4\n" \
+	       "adcs %2, %2, %5\n" \
+	       "adc  %3, %3, %6\n" \
+	       : "+r" (__carry), "+r" (A2), "+r" (A3), "+r" (A4) \
+	       : "r" (B2), "r" (B3), "r" (B4) \
+	       : "cc" ); \
+    } while (0)
+#endif
 
 #endif /* HAVE_COMPATIBLE_GCC_ARM_PLATFORM_AS */
 
-- 
2.32.0




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