[PATCH] mpi: Drop casts from inline asm output operands.
Matt Turner
mattst88 at gmail.com
Wed Sep 2 15:17:20 CEST 2026
* mpi/longlong.h [__a29k__, __alpha, __gmicro__, __hppa, __i960__,
__mc68000__, __m88000__, __mips__, __mips, __ns32000__, __pyr__,
__ibm032__, __sh2__, __sparc__, __vax__, __z8000__]: Drop the casts on
asm output operands.
--
Using a cast as an lvalue is a GCC extension that clang does not
implement. Clang rejects it with -Winvalid-gnu-asm-cast, which is an
error by default, so these blocks fail to build with clang.
The casts do nothing. GCC accepts a cast in an asm output only when it
is a no-op, and rejects it with "lvalue required in 'asm' statement"
otherwise, so any code that compiles today already passes an operand of
the right type. GMP's longlong.h dropped these long ago.
The Z8000 block is the exception. There W_TYPE_SIZE is 16, so the cast
to unsigned int is not a no-op and GCC would reject it too; that block
has been dead for a long time and is fixed here for consistency.
Casts on *input* operands are left alone: those are ordinary rvalue
conversions, and on x86 count_leading_zeros/count_trailing_zeros the
"rm" ((USItype)(x)) cast is what selects the operand width.
Checked with the cross toolchains available here. GCC generates
identical assembly before and after for alpha, hppa, mc68000, sh4,
32-bit sparc and mips. Clang builds the sparc block only after this
change; it has no back end for alpha, hppa or mc68000, so those could
not be checked with clang.
The blocks with no compiler to test against (a29k, gmicro, i960, m88k,
ns32000, pyr, RT/ROMP, vax, z8000) are changed mechanically. The MIPS
asm blocks are unreachable in practice: any compiler new enough to
matter takes the preceding __GNUC__ >= 5 branch, which uses a plain
wide multiply, and the asm variants no longer assemble anyway now that
GCC has removed the "h" constraint ("impossible constraint in 'asm'").
Signed-off-by: Matt Turner <mattst88 at gmail.com>
---
mpi/longlong.h | 174 ++++++++++++++++++++++++-------------------------
1 file changed, 87 insertions(+), 87 deletions(-)
diff --git ./mpi/longlong.h ./mpi/longlong.h
index 453f2704..b27d0b88 100644
--- ./mpi/longlong.h
+++ ./mpi/longlong.h
@@ -133,8 +133,8 @@ SPDX-License-Identifier: LGPL-2.1-or-later
# define add_ssaaaa(sh, sl, ah, al, bh, bl) \
__asm__ ("add %1,%4,%5\n" \
"addc %0,%2,%3" \
- : "=r" ((USItype)(sh)), \
- "=&r" ((USItype)(sl)) \
+ : "=r" (sh), \
+ "=&r" (sl) \
: "%r" ((USItype)(ah)), \
"rI" ((USItype)(bh)), \
"%r" ((USItype)(al)), \
@@ -142,8 +142,8 @@ SPDX-License-Identifier: LGPL-2.1-or-later
# define sub_ddmmss(sh, sl, ah, al, bh, bl) \
__asm__ ("sub %1,%4,%5\n" \
"subc %0,%2,%3" \
- : "=r" ((USItype)(sh)), \
- "=&r" ((USItype)(sl)) \
+ : "=r" (sh), \
+ "=&r" (sl) \
: "r" ((USItype)(ah)), \
"rI" ((USItype)(bh)), \
"r" ((USItype)(al)), \
@@ -152,24 +152,24 @@ SPDX-License-Identifier: LGPL-2.1-or-later
do { \
USItype __m0 = (m0), __m1 = (m1); \
__asm__ ("multiplu %0,%1,%2" \
- : "=r" ((USItype)(xl)) \
+ : "=r" (xl) \
: "r" (__m0), \
"r" (__m1)); \
__asm__ ("multmu %0,%1,%2" \
- : "=r" ((USItype)(xh)) \
+ : "=r" (xh) \
: "r" (__m0), \
"r" (__m1)); \
} while (0)
# define udiv_qrnnd(q, r, n1, n0, d) \
__asm__ ("dividu %0,%3,%4" \
- : "=r" ((USItype)(q)), \
- "=q" ((USItype)(r)) \
+ : "=r" (q), \
+ "=q" (r) \
: "1" ((USItype)(n1)), \
"r" ((USItype)(n0)), \
"r" ((USItype)(d)))
# define count_leading_zeros(count, x) \
__asm__ ("clz %0,%1" \
- : "=r" ((USItype)(count)) \
+ : "=r" (count) \
: "r" ((USItype)(x)))
# define COUNT_LEADING_ZEROS_0 32
#endif /* __a29k__ */
@@ -180,7 +180,7 @@ SPDX-License-Identifier: LGPL-2.1-or-later
do { \
UDItype __m0 = (m0), __m1 = (m1); \
__asm__ ("umulh %r1,%2,%0" \
- : "=r" ((UDItype)(ph)) \
+ : "=r" (ph) \
: "%rJ" (__m0), \
"rI" (__m1)); \
(pl) = __m0 * __m1; \
@@ -365,8 +365,8 @@ extern UDItype __udiv_qrnnd (UDItype *, UDItype, UDItype, UDItype);
# define add_ssaaaa(sh, sl, ah, al, bh, bl) \
__asm__ ("add.w %5,%1\n" \
"addx %3,%0" \
- : "=g" ((USItype)(sh)), \
- "=&g" ((USItype)(sl)) \
+ : "=g" (sh), \
+ "=&g" (sl) \
: "%0" ((USItype)(ah)), \
"g" ((USItype)(bh)), \
"%1" ((USItype)(al)), \
@@ -374,22 +374,22 @@ extern UDItype __udiv_qrnnd (UDItype *, UDItype, UDItype, UDItype);
# define sub_ddmmss(sh, sl, ah, al, bh, bl) \
__asm__ ("sub.w %5,%1\n" \
"subx %3,%0" \
- : "=g" ((USItype)(sh)), \
- "=&g" ((USItype)(sl)) \
+ : "=g" (sh), \
+ "=&g" (sl) \
: "0" ((USItype)(ah)), \
"g" ((USItype)(bh)), \
"1" ((USItype)(al)), \
"g" ((USItype)(bl)))
# define umul_ppmm(ph, pl, m0, m1) \
__asm__ ("mulx %3,%0,%1" \
- : "=g" ((USItype)(ph)), \
- "=r" ((USItype)(pl)) \
+ : "=g" (ph), \
+ "=r" (pl) \
: "%0" ((USItype)(m0)), \
"g" ((USItype)(m1)))
# define udiv_qrnnd(q, r, nh, nl, d) \
__asm__ ("divx %4,%0,%1" \
- : "=g" ((USItype)(q)), \
- "=r" ((USItype)(r)) \
+ : "=g" (q), \
+ "=r" (r) \
: "1" ((USItype)(nh)), \
"0" ((USItype)(nl)), \
"g" ((USItype)(d)))
@@ -408,8 +408,8 @@ extern UDItype __udiv_qrnnd (UDItype *, UDItype, UDItype, UDItype);
# define add_ssaaaa(sh, sl, ah, al, bh, bl) \
__asm__ ("add %4,%5,%1\n\t" \
"addc %2,%3,%0" \
- : "=r" ((USItype)(sh)), \
- "=&r" ((USItype)(sl)) \
+ : "=r" (sh), \
+ "=&r" (sl) \
: "%rM" ((USItype)(ah)), \
"rM" ((USItype)(bh)), \
"%rM" ((USItype)(al)), \
@@ -417,8 +417,8 @@ extern UDItype __udiv_qrnnd (UDItype *, UDItype, UDItype, UDItype);
# define sub_ddmmss(sh, sl, ah, al, bh, bl) \
__asm__ ("sub %4,%5,%1\n\t" \
"subb %2,%3,%0" \
- : "=r" ((USItype)(sh)), \
- "=&r" ((USItype)(sl)) \
+ : "=r" (sh), \
+ "=&r" (sl) \
: "rM" ((USItype)(ah)), \
"rM" ((USItype)(bh)), \
"rM" ((USItype)(al)), \
@@ -658,8 +658,8 @@ extern USItype __udiv_qrnnd (USItype *, USItype, USItype, USItype);
__asm__ ("cmpo 1,0\n" \
"addc %5,%4,%1\n" \
"addc %3,%2,%0" \
- : "=r" ((USItype)(sh)), \
- "=&r" ((USItype)(sl)) \
+ : "=r" (sh), \
+ "=&r" (sl) \
: "%dI" ((USItype)(ah)), \
"dI" ((USItype)(bh)), \
"%dI" ((USItype)(al)), \
@@ -668,8 +668,8 @@ extern USItype __udiv_qrnnd (USItype *, USItype, USItype, USItype);
__asm__ ("cmpo 0,0\n" \
"subc %5,%4,%1\n" \
"subc %3,%2,%0" \
- : "=r" ((USItype)(sh)), \
- "=&r" ((USItype)(sl)) \
+ : "=r" (sh), \
+ "=&r" (sl) \
: "dI" ((USItype)(ah)), \
"dI" ((USItype)(bh)), \
"dI" ((USItype)(al)), \
@@ -733,8 +733,8 @@ extern USItype __udiv_qrnnd (USItype *, USItype, USItype, USItype);
# define add_ssaaaa(sh, sl, ah, al, bh, bl) \
__asm__ ("add%.l %5,%1\n" \
"addx%.l %3,%0" \
- : "=d" ((USItype)(sh)), \
- "=&d" ((USItype)(sl)) \
+ : "=d" (sh), \
+ "=&d" (sl) \
: "%0" ((USItype)(ah)), \
"d" ((USItype)(bh)), \
"%1" ((USItype)(al)), \
@@ -742,8 +742,8 @@ extern USItype __udiv_qrnnd (USItype *, USItype, USItype, USItype);
# define sub_ddmmss(sh, sl, ah, al, bh, bl) \
__asm__ ("sub%.l %5,%1\n" \
"subx%.l %3,%0" \
- : "=d" ((USItype)(sh)), \
- "=&d" ((USItype)(sl)) \
+ : "=d" (sh), \
+ "=&d" (sl) \
: "0" ((USItype)(ah)), \
"d" ((USItype)(bh)), \
"1" ((USItype)(al)), \
@@ -751,29 +751,29 @@ extern USItype __udiv_qrnnd (USItype *, USItype, USItype, USItype);
# if (defined (__mc68020__) || defined (__NeXT__) || defined(mc68020))
# define umul_ppmm(w1, w0, u, v) \
__asm__ ("mulu%.l %3,%1:%0" \
- : "=d" ((USItype)(w0)), \
- "=d" ((USItype)(w1)) \
+ : "=d" (w0), \
+ "=d" (w1) \
: "%0" ((USItype)(u)), \
"dmi" ((USItype)(v)))
# define UMUL_TIME 45
# define udiv_qrnnd(q, r, n1, n0, d) \
__asm__ ("divu%.l %4,%1:%0" \
- : "=d" ((USItype)(q)), \
- "=d" ((USItype)(r)) \
+ : "=d" (q), \
+ "=d" (r) \
: "0" ((USItype)(n0)), \
"1" ((USItype)(n1)), \
"dmi" ((USItype)(d)))
# define UDIV_TIME 90
# define sdiv_qrnnd(q, r, n1, n0, d) \
__asm__ ("divs%.l %4,%1:%0" \
- : "=d" ((USItype)(q)), \
- "=d" ((USItype)(r)) \
+ : "=d" (q), \
+ "=d" (r) \
: "0" ((USItype)(n0)), \
"1" ((USItype)(n1)), \
"dmi" ((USItype)(d)))
# define count_leading_zeros(count, x) \
__asm__ ("bfffo %1{%b2:%b2},%0" \
- : "=d" ((USItype)(count)) \
+ : "=d" (count) \
: "od" ((USItype)(x)), "n" (0))
# define COUNT_LEADING_ZEROS_0 32
# else /* not mc68020 */
@@ -801,7 +801,7 @@ extern USItype __udiv_qrnnd (USItype *, USItype, USItype, USItype);
" add%.l %3,%1 \n" \
" addx%.l %2,%0 \n" \
" | End inlined umul_ppmm" \
- : "=&d" ((USItype)(xh)), "=&d" ((USItype)(xl)), \
+ : "=&d" (xh), "=&d" (xl), \
"=d" (__umul_tmp1), "=&d" (__umul_tmp2) \
: "%2" ((USItype)(a)), "d" ((USItype)(b))); \
} while (0)
@@ -818,8 +818,8 @@ extern USItype __udiv_qrnnd (USItype *, USItype, USItype, USItype);
# define add_ssaaaa(sh, sl, ah, al, bh, bl) \
__asm__ ("addu.co %1,%r4,%r5\n" \
"addu.ci %0,%r2,%r3" \
- : "=r" ((USItype)(sh)), \
- "=&r" ((USItype)(sl)) \
+ : "=r" (sh), \
+ "=&r" (sl) \
: "%rJ" ((USItype)(ah)), \
"rJ" ((USItype)(bh)), \
"%rJ" ((USItype)(al)), \
@@ -827,8 +827,8 @@ extern USItype __udiv_qrnnd (USItype *, USItype, USItype, USItype);
# define sub_ddmmss(sh, sl, ah, al, bh, bl) \
__asm__ ("subu.co %1,%r4,%r5\n" \
"subu.ci %0,%r2,%r3" \
- : "=r" ((USItype)(sh)), \
- "=&r" ((USItype)(sl)) \
+ : "=r" (sh), \
+ "=&r" (sl) \
: "rJ" ((USItype)(ah)), \
"rJ" ((USItype)(bh)), \
"rJ" ((USItype)(al)), \
@@ -884,8 +884,8 @@ extern USItype __udiv_qrnnd (USItype *, USItype, USItype, USItype);
# elif __GNUC__ > 2 || __GNUC_MINOR__ >= 7
# define umul_ppmm(w1, w0, u, v) \
__asm__ ("multu %2,%3" \
- : "=l" ((USItype)(w0)), \
- "=h" ((USItype)(w1)) \
+ : "=l" (w0), \
+ "=h" (w1) \
: "d" ((USItype)(u)), \
"d" ((USItype)(v)))
# else
@@ -893,8 +893,8 @@ extern USItype __udiv_qrnnd (USItype *, USItype, USItype, USItype);
__asm__ ("multu %2,%3 \n" \
"mflo %0 \n" \
"mfhi %1" \
- : "=d" ((USItype)(w0)), \
- "=d" ((USItype)(w1)) \
+ : "=d" (w0), \
+ "=d" (w1) \
: "d" ((USItype)(u)), \
"d" ((USItype)(v)))
# endif
@@ -919,8 +919,8 @@ typedef unsigned int UTItype __attribute__ ((mode (TI)));
# elif __GNUC__ > 2 || __GNUC_MINOR__ >= 7
# define umul_ppmm(w1, w0, u, v) \
__asm__ ("dmultu %2,%3" \
- : "=l" ((UDItype)(w0)), \
- "=h" ((UDItype)(w1)) \
+ : "=l" (w0), \
+ "=h" (w1) \
: "d" ((UDItype)(u)), \
"d" ((UDItype)(v)))
# else
@@ -928,8 +928,8 @@ typedef unsigned int UTItype __attribute__ ((mode (TI)));
__asm__ ("dmultu %2,%3 \n" \
"mflo %0 \n" \
"mfhi %1" \
- : "=d" ((UDItype)(w0)), \
- "=d" ((UDItype)(w1)) \
+ : "=d" (w0), \
+ "=d" (w1) \
: "d" ((UDItype)(u)), \
"d" ((UDItype)(v)))
# endif
@@ -971,7 +971,7 @@ typedef unsigned int UTItype __attribute__ ((mode (TI)));
# define count_trailing_zeros(count,x) \
do {
__asm__ ("ffsd %2,%0" \
- : "=r" ((USItype) (count)) \
+ : "=r" (count) \
: "0" ((USItype) 0), \
"r" ((USItype) (x))); \
} while (0)
@@ -1120,8 +1120,8 @@ typedef unsigned int UTItype __attribute__ ((mode (TI)));
# define add_ssaaaa(sh, sl, ah, al, bh, bl) \
__asm__ ("addw %5,%1 \n" \
"addwc %3,%0" \
- : "=r" ((USItype)(sh)), \
- "=&r" ((USItype)(sl)) \
+ : "=r" (sh), \
+ "=&r" (sl) \
: "%0" ((USItype)(ah)), \
"g" ((USItype)(bh)), \
"%1" ((USItype)(al)), \
@@ -1129,8 +1129,8 @@ typedef unsigned int UTItype __attribute__ ((mode (TI)));
# define sub_ddmmss(sh, sl, ah, al, bh, bl) \
__asm__ ("subw %5,%1 \n" \
"subwb %3,%0" \
- : "=r" ((USItype)(sh)), \
- "=&r" ((USItype)(sl)) \
+ : "=r" (sh), \
+ "=&r" (sl) \
: "0" ((USItype)(ah)), \
"g" ((USItype)(bh)), \
"1" ((USItype)(al)), \
@@ -1156,8 +1156,8 @@ typedef unsigned int UTItype __attribute__ ((mode (TI)));
# define add_ssaaaa(sh, sl, ah, al, bh, bl) \
__asm__ ("a %1,%5 \n" \
"ae %0,%3" \
- : "=r" ((USItype)(sh)), \
- "=&r" ((USItype)(sl)) \
+ : "=r" (sh), \
+ "=&r" (sl) \
: "%0" ((USItype)(ah)), \
"r" ((USItype)(bh)), \
"%1" ((USItype)(al)), \
@@ -1165,8 +1165,8 @@ typedef unsigned int UTItype __attribute__ ((mode (TI)));
# define sub_ddmmss(sh, sl, ah, al, bh, bl) \
__asm__ ("s %1,%5\n" \
"se %0,%3" \
- : "=r" ((USItype)(sh)), \
- "=&r" ((USItype)(sl)) \
+ : "=r" (sh), \
+ "=&r" (sl) \
: "0" ((USItype)(ah)), \
"r" ((USItype)(bh)), \
"1" ((USItype)(al)), \
@@ -1195,8 +1195,8 @@ typedef unsigned int UTItype __attribute__ ((mode (TI)));
"m r2,%3 \n" \
"cas %0,r2,r0 \n" \
"mfs r10,%1" \
- : "=r" ((USItype)(ph)), \
- "=r" ((USItype)(pl)) \
+ : "=r" (ph), \
+ "=r" (pl) \
: "%r" (__m0), \
"r" (__m1) \
: "r2"); \
@@ -1209,12 +1209,12 @@ typedef unsigned int UTItype __attribute__ ((mode (TI)));
do { \
if ((x) >= 0x10000) \
__asm__ ("clz %0,%1" \
- : "=r" ((USItype)(count)) \
+ : "=r" (count) \
: "r" ((USItype)(x) >> 16)); \
else \
{ \
__asm__ ("clz %0,%1" \
- : "=r" ((USItype)(count)) \
+ : "=r" (count) \
: "r" ((USItype)(x))); \
(count) += 16; \
} \
@@ -1232,8 +1232,8 @@ typedef unsigned int UTItype __attribute__ ((mode (TI)));
"dmulu.l %2,%3\n" \
"sts macl,%1\n" \
"sts mach,%0" \
- : "=r" ((USItype)(w1)), \
- "=r" ((USItype)(w0)) \
+ : "=r" (w1), \
+ "=r" (w0) \
: "r" ((USItype)(u)), \
"r" ((USItype)(v)) \
: "macl", "mach")
@@ -1247,8 +1247,8 @@ typedef unsigned int UTItype __attribute__ ((mode (TI)));
# define add_ssaaaa(sh, sl, ah, al, bh, bl) \
__asm__ ("addcc %r4,%5,%1\n" \
"addx %r2,%3,%0" \
- : "=r" ((USItype)(sh)), \
- "=&r" ((USItype)(sl)) \
+ : "=r" (sh), \
+ "=&r" (sl) \
: "%rJ" ((USItype)(ah)), \
"rI" ((USItype)(bh)), \
"%rJ" ((USItype)(al)), \
@@ -1257,8 +1257,8 @@ typedef unsigned int UTItype __attribute__ ((mode (TI)));
# define sub_ddmmss(sh, sl, ah, al, bh, bl) \
__asm__ ("subcc %r4,%5,%1\n" \
"subx %r2,%3,%0" \
- : "=r" ((USItype)(sh)), \
- "=&r" ((USItype)(sl)) \
+ : "=r" (sh), \
+ "=&r" (sl) \
: "rJ" ((USItype)(ah)), \
"rI" ((USItype)(bh)), \
"rJ" ((USItype)(al)), \
@@ -1271,8 +1271,8 @@ typedef unsigned int UTItype __attribute__ ((mode (TI)));
but INTERPRETED AS UNSIGNED. */
# define umul_ppmm(w1, w0, u, v) \
__asm__ ("umul %2,%3,%1;rd %%y,%0" \
- : "=r" ((USItype)(w1)), \
- "=r" ((USItype)(w0)) \
+ : "=r" (w1), \
+ "=r" (w0) \
: "r" ((USItype)(u)), \
"r" ((USItype)(v)))
# define UMUL_TIME 5
@@ -1281,7 +1281,7 @@ typedef unsigned int UTItype __attribute__ ((mode (TI)));
do { \
USItype __q; \
__asm__ ("mov %1,%%y;nop;nop;nop;udiv %2,%3,%0" \
- : "=r" ((USItype)(__q)) \
+ : "=r" (__q) \
: "r" ((USItype)(n1)), \
"r" ((USItype)(n0)), \
"r" ((USItype)(d))); \
@@ -1296,8 +1296,8 @@ typedef unsigned int UTItype __attribute__ ((mode (TI)));
instructions scan (ffs from high bit) and divscc. */
# define umul_ppmm(w1, w0, u, v) \
__asm__ ("umul %2,%3,%1;rd %%y,%0" \
- : "=r" ((USItype)(w1)), \
- "=r" ((USItype)(w0)) \
+ : "=r" (w1), \
+ "=r" (w0) \
: "r" ((USItype)(u)), \
"r" ((USItype)(v)))
# define UMUL_TIME 5
@@ -1341,8 +1341,8 @@ typedef unsigned int UTItype __attribute__ ((mode (TI)));
" bl,a 1f \n" \
" add %1,%4,%1 \n" \
"1: ! End of inline udiv_qrnnd" \
- : "=r" ((USItype)(q)), \
- "=r" ((USItype)(r)) \
+ : "=r" (q), \
+ "=r" (r) \
: "r" ((USItype)(n1)), \
"r" ((USItype)(n0)), \
"rI" ((USItype)(d)) \
@@ -1350,7 +1350,7 @@ typedef unsigned int UTItype __attribute__ ((mode (TI)));
# define UDIV_TIME 37
# define count_leading_zeros(count, x) \
__asm__ ("scan %1,0,%0" \
- : "=r" ((USItype)(x)) \
+ : "=r" (x) \
: "r" ((USItype)(count)))
/* Early sparclites return 63 for an argument of 0, but they warn that future
implementations might change this. Therefore, leave COUNT_LEADING_ZEROS_0
@@ -1400,8 +1400,8 @@ typedef unsigned int UTItype __attribute__ ((mode (TI)));
" mulscc %%g1,0,%%g1 \n" \
" add %%g1,%%g2,%0 \n" \
" rd %%y,%1" \
- : "=r" ((USItype)(w1)), \
- "=r" ((USItype)(w0)) \
+ : "=r" (w1), \
+ "=r" (w0) \
: "%rI" ((USItype)(u)), \
"r" ((USItype)(v)) \
: "%g1", "%g2" __AND_CLOBBER_CC)
@@ -1428,8 +1428,8 @@ extern USItype __udiv_qrnnd (USItype *, USItype, USItype, USItype);
# define add_ssaaaa(sh, sl, ah, al, bh, bl) \
__asm__ ("addl2 %5,%1\n" \
"adwc %3,%0" \
- : "=g" ((USItype)(sh)), \
- "=&g" ((USItype)(sl)) \
+ : "=g" (sh), \
+ "=&g" (sl) \
: "%0" ((USItype)(ah)), \
"g" ((USItype)(bh)), \
"%1" ((USItype)(al)), \
@@ -1437,8 +1437,8 @@ extern USItype __udiv_qrnnd (USItype *, USItype, USItype, USItype);
# define sub_ddmmss(sh, sl, ah, al, bh, bl) \
__asm__ ("subl2 %5,%1\n" \
"sbwc %3,%0" \
- : "=g" ((USItype)(sh)), \
- "=&g" ((USItype)(sl)) \
+ : "=g" (sh), \
+ "=&g" (sl) \
: "0" ((USItype)(ah)), \
"g" ((USItype)(bh)), \
"1" ((USItype)(al)), \
@@ -1476,16 +1476,16 @@ extern USItype __udiv_qrnnd (USItype *, USItype, USItype, USItype);
#if defined (__z8000__) && W_TYPE_SIZE == 16
# define add_ssaaaa(sh, sl, ah, al, bh, bl) \
__asm__ ("add %H1,%H5\n\tadc %H0,%H3" \
- : "=r" ((unsigned int)(sh)), \
- "=&r" ((unsigned int)(sl)) \
+ : "=r" (sh), \
+ "=&r" (sl) \
: "%0" ((unsigned int)(ah)), \
"r" ((unsigned int)(bh)), \
"%1" ((unsigned int)(al)), \
"rQR" ((unsigned int)(bl)))
# define sub_ddmmss(sh, sl, ah, al, bh, bl) \
__asm__ ("sub %H1,%H5\n\tsbc %H0,%H3" \
- : "=r" ((unsigned int)(sh)), \
- "=&r" ((unsigned int)(sl)) \
+ : "=r" (sh), \
+ "=&r" (sl) \
: "0" ((unsigned int)(ah)), \
"r" ((unsigned int)(bh)), \
"1" ((unsigned int)(al)), \
--
2.54.0
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