[git] GCRYPT - branch, master, updated. libgcrypt-1.7.0-6-g3e8074e
by Jérémie Courrèges-Anglas
cvs at cvs.gnupg.org
Sat May 28 12:05:10 CEST 2016
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- Log -----------------------------------------------------------------
commit 3e8074ecd3a534e8bd7f11cf17f0b22d252584c8
Author: Jérémie Courrèges-Anglas <jca at wxcvbn.org>
Date: Mon May 9 04:04:59 2016 +0200
Check for compiler SSE4.1 support in PCLMUL CRC code.
* cipher/crc-intel-pclmul.c: Build PCLMUL CRC implementation only if
compiler supports PCLMUL *and* SSE4.1
* cipher/crc.c: Ditto
* configure.ac (sse41support, gcry_cv_gcc_inline_asm_sse41): New.
--
Fixes build with the native gcc on OpenBSD/amd64, which supports PCLMUL
but not SSE4.1.
Signed-off-by: Jérémie Courrèges-Anglas <jca at wxcvbn.org>
diff --git a/cipher/crc-intel-pclmul.c b/cipher/crc-intel-pclmul.c
index c034e2e..2972fb4 100644
--- a/cipher/crc-intel-pclmul.c
+++ b/cipher/crc-intel-pclmul.c
@@ -30,7 +30,8 @@
#include "bufhelp.h"
-#if defined(ENABLE_PCLMUL_SUPPORT) && __GNUC__ >= 4 && \
+#if defined(ENABLE_PCLMUL_SUPPORT) && defined(ENABLE_SSE41_SUPPORT) && \
+ __GNUC__ >= 4 && \
((defined(__i386__) && SIZEOF_UNSIGNED_LONG == 4) || defined(__x86_64__))
diff --git a/cipher/crc.c b/cipher/crc.c
index ee0e4e2..a1ce50b 100644
--- a/cipher/crc.c
+++ b/cipher/crc.c
@@ -31,10 +31,10 @@
#include "bufhelp.h"
-/* USE_INTEL_PCLMUL indicates whether to compile CRC with Intel PCLMUL
+/* USE_INTEL_PCLMUL indicates whether to compile CRC with Intel PCLMUL/SSE4.1
* code. */
#undef USE_INTEL_PCLMUL
-#ifdef ENABLE_PCLMUL_SUPPORT
+#if defined(ENABLE_PCLMUL_SUPPORT) && defined(ENABLE_SSE41_SUPPORT)
# if ((defined(__i386__) && SIZEOF_UNSIGNED_LONG == 4) || defined(__x86_64__))
# if __GNUC__ >= 4
# define USE_INTEL_PCLMUL 1
diff --git a/configure.ac b/configure.ac
index ad06dfd..ad0f64d 100644
--- a/configure.ac
+++ b/configure.ac
@@ -597,6 +597,14 @@ AC_ARG_ENABLE(pclmul-support,
pclmulsupport=$enableval,pclmulsupport=yes)
AC_MSG_RESULT($pclmulsupport)
+# Implementation of the --disable-sse41-support switch.
+AC_MSG_CHECKING([whether SSE4.1 support is requested])
+AC_ARG_ENABLE(sse41-support,
+ AC_HELP_STRING([--disable-sse41-support],
+ [Disable support for the Intel SSE4.1 instructions]),
+ sse41support=$enableval,sse41support=yes)
+AC_MSG_RESULT($sse41support)
+
# Implementation of the --disable-drng-support switch.
AC_MSG_CHECKING([whether DRNG support is requested])
AC_ARG_ENABLE(drng-support,
@@ -1109,6 +1117,7 @@ AM_CONDITIONAL(MPI_MOD_C_UDIV_QRNND, test "$mpi_mod_c_udiv_qrnnd" = yes)
if test "$mpi_cpu_arch" != "x86" ; then
aesnisupport="n/a"
pclmulsupport="n/a"
+ sse41support="n/a"
avxsupport="n/a"
avx2support="n/a"
padlocksupport="n/a"
@@ -1257,6 +1266,27 @@ if test "$gcry_cv_gcc_inline_asm_pclmul" = "yes" ; then
[Defined if inline assembler supports PCLMUL instructions])
fi
+#
+# Check whether GCC inline assembler supports SSE4.1 instructions.
+#
+AC_CACHE_CHECK([whether GCC inline assembler supports SSE4.1 instructions],
+ [gcry_cv_gcc_inline_asm_sse41],
+ [if test "$mpi_cpu_arch" != "x86" ; then
+ gcry_cv_gcc_inline_asm_sse41="n/a"
+ else
+ gcry_cv_gcc_inline_asm_sse41=no
+ AC_COMPILE_IFELSE([AC_LANG_SOURCE(
+ [[void a(void) {
+ int i;
+ __asm__("pextrd \$2, %%xmm0, %[out]\n\t" : [out] "=m" (i));
+ }]])],
+ [gcry_cv_gcc_inline_asm_sse41=yes])
+ fi])
+if test "$gcry_cv_gcc_inline_asm_sse41" = "yes" ; then
+ AC_DEFINE(HAVE_GCC_INLINE_ASM_SSE41,1,
+ [Defined if inline assembler supports SSE4.1 instructions])
+fi
+
#
# Check whether GCC inline assembler supports AVX instructions
@@ -1711,6 +1741,11 @@ if test x"$pclmulsupport" = xyes ; then
pclmulsupport="no (unsupported by compiler)"
fi
fi
+if test x"$sse41support" = xyes ; then
+ if test "$gcry_cv_gcc_inline_asm_sse41" != "yes" ; then
+ sse41support="no (unsupported by compiler)"
+ fi
+fi
if test x"$avxsupport" = xyes ; then
if test "$gcry_cv_gcc_inline_asm_avx" != "yes" ; then
avxsupport="no (unsupported by compiler)"
@@ -1735,6 +1770,10 @@ if test x"$pclmulsupport" = xyes ; then
AC_DEFINE(ENABLE_PCLMUL_SUPPORT, 1,
[Enable support for Intel PCLMUL instructions.])
fi
+if test x"$sse41support" = xyes ; then
+ AC_DEFINE(ENABLE_SSE41_SUPPORT, 1,
+ [Enable support for Intel SSE4.1 instructions.])
+fi
if test x"$avxsupport" = xyes ; then
AC_DEFINE(ENABLE_AVX_SUPPORT,1,
[Enable support for Intel AVX instructions.])
@@ -2340,6 +2379,7 @@ GCRY_MSG_SHOW([Using linux capabilities: ],[$use_capabilities])
GCRY_MSG_SHOW([Try using Padlock crypto: ],[$padlocksupport])
GCRY_MSG_SHOW([Try using AES-NI crypto: ],[$aesnisupport])
GCRY_MSG_SHOW([Try using Intel PCLMUL: ],[$pclmulsupport])
+GCRY_MSG_SHOW([Try using Intel SSE4.1: ],[$sse41support])
GCRY_MSG_SHOW([Try using DRNG (RDRAND): ],[$drngsupport])
GCRY_MSG_SHOW([Try using Intel AVX: ],[$avxsupport])
GCRY_MSG_SHOW([Try using Intel AVX2: ],[$avx2support])
commit eb6427c3b5993d62e0527b8a08b23a219824b965
Author: Jussi Kivilinna <jussi.kivilinna at iki.fi>
Date: Sat May 28 12:59:54 2016 +0300
Register DCO for Jérémie Courrèges-Anglas
--
Signed-off-by: Jussi Kivilinna <jussi.kivilinna at iki.fi>
diff --git a/AUTHORS b/AUTHORS
index f89d585..25de16c 100644
--- a/AUTHORS
+++ b/AUTHORS
@@ -156,6 +156,9 @@ Dmitry Eremin-Solenikov <dbaryshkov at gmail.com>
Dmitry Kasatkin <dmitry.kasatkin at intel.com>
2012-12-14:50CAE2DB.80302 at intel.com:
+Jérémie Courrèges-Anglas <jca at wxcvbn.org>
+2016-05-26:87bn3ssqg0.fsf at ritchie.wxcvbn.org:
+
Jussi Kivilinna <jussi.kivilinna at mbnet.fi>
2012-11-15:20121115172331.150537dzb5i6jmy8 at www.dalek.fi:
-----------------------------------------------------------------------
Summary of changes:
AUTHORS | 3 +++
cipher/crc-intel-pclmul.c | 3 ++-
cipher/crc.c | 4 ++--
configure.ac | 40 ++++++++++++++++++++++++++++++++++++++++
4 files changed, 47 insertions(+), 3 deletions(-)
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